Contemporary memory devices typically include an array of memory cells arranged in rows and columns. Memory cells of each row are accessed by activating a corresponding access line often referred to as a word line. The word line may be activated by a word line driver responsive to decoding a corresponding row address with a row address decoder.
Word line drivers typically comprise a p-channel field effect transistor (pFET) and an n-channel field effect transistor (nFET) coupled together at their respective drains and gates, thrilling a complementary FET output stage coupled to the word line at the drains of the transistors. The source of the pFET can be configured to receive, for example, a phase signal (e.g., from a phase decoder). Meanwhile, the source of the nFET can be configured to receive, for example, a deactivated word line voltage (e.g., VNEGWL). Assuming a sufficiently high voltage phase signal (e.g., VCCP, which may be a pumped supply voltage) is provided as the phase signal to the source of its word line driver, a word line may be activated by providing a sufficiently low voltage (e.g., ground) to the gate of the pFET to turn on the pFET and pull the word line up to ˜VCCP. To quickly deactivate the word line (e.g., to close the row), as is typically desired after a row of memory cells has been accessed (e.g., refreshed), a sufficiently high voltage (e.g., VCCP) is provided to the gate of the nFET to quickly turn on the nFET and pull the word line down to ˜VNEGWL.
A performance issue associated with the use of such a word line driver is gate-induced diode leakage (GIDL) current. GIDL currents may arise when the pFET of a word line driver experiences a relatively significant gate-to-drain voltage such that current leaks from the nwell to the drain of the pFET when the transistor is operating in an “off” state. Since the gates of the pFET and nFET transistors are coupled together in such to word line driver, this can occur when VCCP is being provided to the gate of the nFET (and thus also to the gate of the pFET). Because numerous word line drivers may be used simultaneously in a memory system, GIDL current can result in substantial unwanted power consumption, even in inactive sections of memory.
Some design considerations have been implemented in an attempt to mitigate power consumption resulting from GIDL currents. One method involves reducing the voltage being provided to the gate of the nFET after the word line has been deactivated, such as by discharging the voltage being provided to the gate of the nFET down to VCC (where VCC may be as common supply voltage) after deactivating the word line. In some embodiments, the VCCP voltage is greater than the VCC voltage by about 2 volts, for example (e.g., the VCC voltage may be about 1.2 volts and the VCCP voltage may be about 3.2 volts). The VCCP and VCC voltages may have other voltage magnitudes as well, and may also have different voltage differences.
The aforementioned method to mitigate power consumption resulting from GIDL current requires charging/discharging the voltage on a node (Vccprdec) of a memory section control circuit between VCC and VCCP. During some memory operations, for example, a self refresh operation, rows of memory are typically sequentially accessed, causing repeated charging and discharging of the Vccprdec node as the rows of an active section of memory are refreshed. Like GIDL currents, this frequent charging and discharging between the reduced voltage and the increased voltage can lead to unwanted consumption of current.
Therefore, a need exists for a method and system to refresh memory cells that may decrease power consumption resulting from GIDL currents.